Review of Ethernet SGMII (8B/10B SERDES) Concepts (2024)

Overview

This article reviews various SGMII (& 1000BASE-SX) concepts thatare integral to our Private Island ®project and its soft Verilog MAC layer. We provide oscilloscope screen shotsbelow to help illustrate the concepts.

As shown in the block diagram below, Private Island utilizes a SERDEScapable FPGA, such as the Intel Cyclone 10 GX on our company's Volitio™ board, tointerface with SGMII Gigabit Ethernet PHYs and other SERDES-basedperipherals.

Unlike a typical SoC, an FPGA is capable of asserting an externalinterrupt synchronous to specific packet transmit or receive events.The interrupt can also assert on specific octets / special codes withinthe Ethernet frame (i.e., end of packet). This interrupt flexibility isimportant for certain security functions and provides a reliable andpredictable way to trigger our scope during debug of the SGMII / SERDESbus for both hardware and software debug.

For the oscilloscope screen shots provided in this article, theFPGA is configured as a transparent bridge between an Ethernet switchand an embedded Linux node. Certain received Ethernet frames from theLAN are mirrored onto a TAP port with the simultaneous assertion of aninterrupt line. As shown in the image below, oscilloscope probes accessthe SGMII tap point via either AC coupling caps or via SMA TXconnectors.

Note that the board on the left is a Gigabit Fiber Media Converter, and the board onthe right is a prototype of a Priviate Island maker board.

Brief overview of popular PHY Interfaces

• GMII, which is specified by IEEE 802.3 defines a separate8-bit bus for transmit and receive data plus several signals to conveyadditional information between the MAC and PHY. GMII is based on MII,which is defined in Clause 22. In addition to the data buses andcontrol signals, GMII requires two 125 MHz bit clocks: GTX_CLK andRX_CLK
• RGMII, which was defined by HP, Broadcom, and Marvell, reducesthe pin count primarily by utilizing double data rate signaling of thedata buses and control, and this enables an SDR 8-bit data bus to berealized as a 4-bit DDR data bus.
• SGMII, which was defined by Cisco, utilizes two pairs ofSERDES / LVDS differential buses to carry transmit and receive data at1.25 Gbps. A differential receive clock is also defined but isoptional and typically not used. Instead, the receive clock isrecovered from the data on the differential pair. The data is encodedusing an 8B/10B coding scheme, which is specified in clause 36 of802.3. The effective bit rate is 8 / 10 * 1.25 Gbps = 1.0 Gbps, as youwould expect. The out-of-band information conveyed by the GMII controlsignals (TX_EN, TX_ER, RX_ER, and RX_DV) are replaced by specialcode-groups (K values). This enables conveying information such asconfiguration, line state, and carrier events between the MAC and PHY.

SGMII Hardware Signaling

The SGMII specification provides its own definition of LVDS, which isderived from IEEE 1596.3-1996. However, the parameters providedin the SGMII specification are defined in the IEEE specification. Forthe purpose of SGMII hardware signaling, these two specifications aresufficient. PHY vendors often refer to this specification rather thanproviding their own numbers. Note that LVDS in general is an industrystandard, and is defined in EIA/TIA-644A. A great resource for LVDS anddifferential signaling is the TI /National LVDS Owners Manual.

The figure below provides a very simple schematic of LVDSsignaling. The concept being conveyed is that the transmitter drives asmall current across a 100 ohm load in the receiver in one of twodirections to produce either a positive or negative voltage across thereceiver (Vod). This small current is superimposed over a commonvoltage (Vos), typically 1.2V. The industry standard LVDS specifies a3.5 mA driver current. The SGMII specification implies it is less since|Vod| max is 400 mV. In practice, most SGMII drivers (e.g., PHYs)support the configuration of multiple drive levels.

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The next figure shows an oscilloscope screen shot of an SGMII bususing a 4.5 GHz differential probe. The probe tips are placed on thetwo AC coupling caps of the differential SGMII bus. The yellow signalis the SGMII signal, and the blue square wave is generated from thescope's HW CDR math function. A probe meter function is shown in thelower right. This is a feature / function of the probe and shows thatthe common mode voltage (Vos) is near 1.2V

The next screen shot shows an SGMII eye diagram with 100 mspersistence enabled. As expected, the unit interval (UI) isapproximately 800 ps. As can be seen in the upper right, the trigger isthe built-in HW CDR.

A Look at SGMII Special Code Groups

Clause 36 of 802.3 defines certain 10-bit values as K values toconvey non-data (out of band) information between the MAC and PHY.These K values take the place of the GMII control signals and specialencodings of the GMII data bus. For Example, /K27.7/ defines a start ofpacket on the SGMII bus.

Referring to 802.3 Table 36-2 (valid special code-groups) and thescreen shot below, we can see that K27.7 is defined as the bit sequence001001 0111 ([a..j] with 'a' transmitted first). This screen shot wastaken using two single ended SMA cables (see figure below) and utilizesthe 8B/10B protocol decode function equipped with our scope. Note thatthat when the orange waveform is positive, the signal is a 1 and whenthe blue waveform is positive the signal is a 0.

The '+' after K27.7 indicates that the 10-bit waveform has acurrently positive running disparity. Each code, both special and data,can either have a current positive or negative running disparity, andthis indicates the difference of the total number of 1's and 0's on thewire. Refer to 802.3 clause 36.2 and Annex 36B for the details onrunning disparity and its rules.

Ordered Sets

802.3 defines ordered sets (Table 36-3) that consist of one ormore code groups, each of which starts with a special code group (Kvalue). For example, /I2/ specifies the IDLE2 line state and is encodedby /K28.5/D16.2/. This waveform continually repeats while the lineremains in a powered up idle state, and is shown in the figure below.

• K28.5-: 001111 1010
• D16.2+: 100100 0101

Data and Packets on an SGMII Bus

The next figure shows a captured packet preamble on an SGMII bus.Per 802.3 35.2.3.2.1 and 36.2.4.14, An /S/ code (start of packetdelimiter, K27.7) replaces the first octet of the preamble followed bythe remaining PREAMBLE/SFD sequence: 0x55 0x55 0x55 0x55 0x55 0x550xD5.

Note in the figure below that the special code groups (K) areshown in blue and the data code groups (D) are shown in yellow.

Our last scope screen shot shows a complete packet captured. The FPGA'sinterrupt line is used to trigger the scope synchronously with thereception of the packet on the TAP port. The scope trace highlights thefunctionality of the 8B/10B protocol decode feature, showing the fulldecode results in a table and a search result box looking for the K27.7special code group, which appears on the SGMII bus 60.46 ns after theinterrupt. This certainly gives new meaning to the term packetinspection.

1000BASE-SX

It's important to note that SGMII is derived from 1000BASE-SX,which is defined in 802.3 Section 3. 1000BASE-SX is a specification forEthernet over Fiber, and it utilizes 8B/10B coding for out of bandsignaling.